FPGA and Silicon Design
We offers FPGA Design, Silicon Design, VLSI Design Services which is performed by experienced designers with an established track record of complex FPGA design, ASIC design and Silicon design. Tattva Electronics commits to provide world-class Products and Services to its Customers in VLSI Products and Technology services area. We are actively working in the area of VLSI Design Services and Have Product Portfolio of many IP’s & VIP's (Verification IP ).
We offer comprehensive design solutions in areas of ASIC, SoC and FPGA. Our diversely skilled VLSI design services team brings various services which include design and development, Test suite development, FPGA design, FPGA validation, FPGA verification and RTL coding.
VLSI Verification Expertise
- Verification Planning
- Test Bench Architecture
- Test Bench Development
- Memory Models
- Protocol Monitors
- Protocol Checkers
- Performance Analysis
- Test case Development
- RTL Debugging and Bug Fixing
- Gate Level Simulations / Netlist Simulations
- Code Coverage and Functional Coverage
IP Design and Verification Services
- RTL Coding in Verilog and VHDL
- Verification Suite development and Automation of the verification environment
- Behavioral model for verification
- IP Integration at SoC Level and Verification
- Synthesis
- RTL/Pre-Layout/post-Layout netlist verification
- Formal Verification: RTL, netlist and at various stages of implementation
- Emulation/Target Board for ASIC/IP validation
Consulting Service Areas
- RTL design
- RTL verification
- RTL synthesis
- DFT
- Physical Design
- Analog and mixed signal
- Analog and mixed signal custom layout
- Pre/Post Silicon Validation
- FPGA Design/Porting
- PCB Design [Design/Layout/Testing]
- Misc- Lib Development, characterization, Modeling, etc
System-Level and FPGA Design
- Systematic and Qualitative approach for FPGA implementations
- Selection of FPGA/CPLD devices for specification, optimum speed/power performance within cost constraints
- Design and Implementation of IP blocks
- Integration of IP blocks and system-level functional simulation
- Mapping Designs to target FPGA/CPLD and physical synthesis
- Expertise in the emulation environment for multi-million gate System On Chip designs
- Exposure to Devices and EDA tools from various vendors
